PCB Via Size Calculator
The finished hole diameter after drilling. Standard range: 0.2–0.5 mm for through-hole.
Standard electroless copper plating is 25 µm (1 mil). Heavy copper is 35–50 µm.
Maximum allowable temperature increase above ambient. IPC default is 10°C; up to 20°C is common for power vias.
Connected to Copper Plane?
Copper planes absorb heat, increasing current rating by ~1.2× per IPC-2152.
Enter Via Dimensions
Fill in the drill diameter, plating thickness, and board thickness to calculate current capacity, resistance, and geometry for your PCB via.
How to Use the PCB Via Size Calculator
Select Via Type and Enter Geometry
Choose through-hole, blind, buried, or microvia from the Via Type dropdown — this selects the correct IPC-2221 formula constants. Then enter the finished drill diameter in millimeters (use the preset buttons for standard sizes), plating thickness (25 µm standard), and board thickness (1.6 mm is the most common 4-layer board). The calculator updates results instantly as you type.
Set Thermal and Electrical Parameters
Enter the allowable temperature rise (10°C is the IPC standard default; up to 20–30°C may be acceptable for power connections) and ambient operating temperature. If you have a current requirement, enter it in the Required Current field to see the pass/fail status and safety margin. For via arrays, enter the number of parallel vias to calculate total current capacity and total resistance.
Check Pad Diameter and Annular Ring
Expand the Pad & Annular Ring section and enter your pad diameter to verify that your annular ring meets IPC-2221 minimums (6 mil external, 4 mil internal). Select the IPC density level matching your board class. The calculator shows the minimum recommended pad diameter for your drill size and IPC level, making it easy to determine the correct pad size during layout.
Review Results and Export
Review current capacity, resistance, voltage drop, power loss, thermal resistance, aspect ratio risk, and the via size comparison chart. Toggle the Copper Plane connection if your via is adjacent to a copper pour to see the IPC-2152 rating. Enable Advanced parameters to see via inductance and capacitance for high-speed designs. Export to CSV for documentation or click Print to generate a printable report.
Frequently Asked Questions
What is the IPC-2221 formula for via current capacity?
The IPC-2221 standard formula for via current capacity is I = k × ΔT^0.44 × A^0.75, where I is the current in amperes, ΔT is the allowable temperature rise above ambient in degrees Celsius, and A is the copper barrel cross-sectional area in square mils. For through-hole vias, k = 0.093. For blind and buried vias (inner-layer copper), k is lower because inner copper dissipates heat less efficiently. The barrel area is calculated as π × drill_diameter × plating_thickness, representing the annular copper ring, not the full hole area. The formula was derived empirically from physical testing of plated-through holes at IPC and is the global industry standard for via sizing.
What aspect ratio should I target for reliable manufacturing?
For standard PCB manufacturing, target an aspect ratio (board thickness ÷ drill diameter) of 8:1 or less. Most PCB fabricators can reliably plate copper into holes with aspect ratios up to 8:1 using standard chemistry. Aspect ratios between 8:1 and 10:1 are achievable but require advanced plating processes and may incur a cost premium. Aspect ratios above 10:1 are difficult to plate uniformly — the barrel center receives insufficient copper, creating thin spots that increase resistance and risk of open failures. For microvias (laser-drilled HDI vias), the target is 0.8:1 or less, with a maximum depth of approximately 0.25 mm. Always confirm the maximum aspect ratio with your specific fabricator before finalizing the design.
How many vias do I need for a power connection?
The minimum number of vias for a power connection depends on the current requirement and the current capacity of each individual via. A good design rule is to size your via array so each via carries no more than 0.5–1 A, providing substantial safety margin. For example, if you need to carry 5 A through a 1.6 mm board with standard 0.3 mm drills and 25 µm plating at a 10°C temperature rise, each via has a capacity of approximately 0.7 A, so you would need at least 8 vias (5 A ÷ 0.7 A = 7.1, round up). Use the Design Vias mode in this calculator to automatically determine the minimum via count for your target current. Arrange power vias in a grid pattern for even current distribution.
What is the difference between IPC-2221 and IPC-2152 current ratings?
IPC-2221 provides conservative current ratings for isolated conductors without accounting for heat spreading to adjacent copper. IPC-2152 is a newer standard that explicitly accounts for copper plane connections, which provide additional heat-sinking and dramatically improve current capacity. When a via barrel contacts or is adjacent to a large copper plane (ground or power plane), the plane absorbs heat dissipated in the via, allowing the via to carry approximately 1.2 times more current than the IPC-2221 rating. Toggle the Copper Plane option in this calculator to see the IPC-2152 rating. Always use IPC-2221 as your baseline for isolated signal vias, and IPC-2152 only for vias directly connected to large copper fills.
What is via inductance and when does it matter?
Via self-inductance is a parasitic property that causes the via to resist changes in current at high frequencies, creating impedance proportional to frequency. The inductance of a via is approximately 0.2 × h × [ln(4h/d) + 1] nanohenries, where h is the via height in millimeters and d is the drill diameter. As a rule of thumb, expect about 1 nH per millimeter of via length in standard FR-4. At 1 GHz, 1 nH produces about 6 ohms of impedance — significant compared to 50-ohm trace impedance. For designs above 500 MHz, via inductance becomes important for signal integrity. Minimize via inductance by using shorter vias (thinner boards or blind vias), larger drill diameters, and via-in-pad techniques. Add the inductance value from this calculator to your simulation models for accurate high-speed analysis.
What is the minimum annular ring, and why does it matter?
The annular ring is the copper ring on a pad that surrounds the via drill hole on each layer. IPC-2221 specifies minimum annular ring widths to ensure reliable manufacturing even when drill registration is slightly off-center. For external layers (Class 2 and 3 boards), the minimum annular ring is 6 mils (0.15 mm). For internal layers and buried vias, the minimum is 4 mils (0.10 mm). If the drill wanders outside this ring during fabrication, the via may lose its electrical connection to that layer — a catastrophic open failure. Tighter fabrication tolerances (IPC Level C) allow smaller pads, which is essential for high-density routing around fine-pitch BGA components. Always leave at least 6 mils of annular ring on external layers to ensure manufacturing yield.