PCB Via Size Calculator
PCB Via Size Calculator
The finished hole diameter after drilling. Standard range: 0.2–0.5 mm for through-hole.
Standard electroless copper plating is 25 µm (1 mil). Heavy copper is 35–50 µm.
Maximum allowable temperature increase above ambient. IPC default is 10°C; up to 20°C is common for power vias.
Connected to Copper Plane?
Copper planes absorb heat, increasing current rating by ~1.2× per IPC-2152.
Enter Via Dimensions
Fill in the drill diameter, plating thickness, and board thickness to calculate current capacity, resistance, and geometry for your PCB via.
IPC-2221 & IPC-2152 current capacity, resistance, and geometry for all via types
Welcome to our free PCB Via Size Calculator, the most comprehensive online via analysis tool available. Designed for PCB designers, electrical engineers, and electronics hobbyists, this calculator uses the IPC-2221 and IPC-2152 industry standards to determine the current carrying capacity, DC resistance, voltage drop, power dissipation, and parasitic properties of PCB vias in seconds. A via is a plated hole drilled through a printed circuit board that creates an electrical connection between copper layers. Vias are one of the most critical yet often overlooked design elements in PCB layout. An undersized via can become a thermal bottleneck, limiting current flow and causing localized heating that may degrade solder joints, burn copper traces, or cause latent failures that only manifest after months of operation in the field. The IPC-2221 standard provides empirical formulas for via current capacity based on the copper barrel cross-sectional area and the allowable temperature rise above ambient. For through-hole vias, the standard formula uses the constants k=0.093, b=0.44, and c=0.75. For blind and buried vias using inner-layer copper, slightly different constants apply. Our calculator applies the correct formula for each via type automatically. Beyond basic current capacity, via design requires attention to several additional parameters. The aspect ratio — the ratio of board thickness to drill diameter — determines whether the via barrel can be reliably copper-plated during manufacturing. Standard fabrication supports aspect ratios up to 10:1, while ratios above 8:1 require advanced plating processes. Microvias used in high-density interconnect (HDI) boards follow a tighter limit of 0.8:1 to ensure proper filling. The annular ring — the ring of copper pad surrounding the drill hole on each layer — must meet IPC-2221 minimums to ensure reliable mechanical and electrical connection. External layers require at least 6 mil (0.15 mm), while internal layers require at least 4 mil (0.10 mm) for Class 2 and Class 3 boards. Our calculator flags when your pad diameter results in an annular ring below IPC minimums. For power supply designers and high-current applications, using via arrays is essential. Multiple parallel vias share current load, reduce total resistance, and lower voltage drop across the connection. This calculator handles via arrays by computing total current capacity, total parallel resistance, and per-via current distribution for arrays of any size. High-frequency and RF designers also need to consider via parasitic effects. Every via has a self-inductance (approximately 1 nH per mm of via length) that can cause signal integrity problems at gigahertz frequencies. Via capacitance, determined by the pad size and antipad clearance, contributes to parasitic loading of high-speed signal paths. Enable the Advanced section of this calculator to obtain inductance and capacitance estimates for your via geometry. IPC-2152 provides an alternative current rating that accounts for the heat-sinking effect of adjacent copper planes. When a via barrel is in contact with or near a copper pour, the plane absorbs additional heat, increasing the via's effective current rating by approximately 1.2 times. Toggle the copper plane option in this calculator to see the IPC-2152 rating alongside the conservative IPC-2221 result. All calculations run entirely in your browser — no data is sent to any server. Results update in real time as you adjust inputs, making it easy to explore trade-offs between via size, plating thickness, number of vias, and temperature rise. Use the comparison chart to visualize how current capacity scales from microvia (0.1 mm) to power via (0.5 mm) sizes, and export your results to CSV for documentation.
Understanding PCB Via Design
PCB vias create electrical connections between layers. Correct sizing ensures reliable current flow, adequate structural integrity, and manufacturable aspect ratios.
IPC-2221 Current Capacity Formula
The IPC-2221 standard uses an empirical formula I = k × ΔT^b × A^c to relate current capacity to the copper barrel cross-sectional area and allowable temperature rise. For through-hole vias, k=0.093, b=0.44, c=0.75. The cross-sectional area is calculated as A = π × D_drill × t_plating in square mils, representing the annular copper barrel wall rather than the full hole area. This formula was derived from physical testing of plated-through holes and is widely accepted by PCB fabricators worldwide. Temperature rise of 10°C is the standard design target, though 20–30°C may be acceptable for non-critical connections.
Aspect Ratio and Manufacturability
Aspect ratio (AR) is the ratio of board thickness to via drill diameter. It is the primary determinant of plating reliability. At AR ≤ 8:1, most PCB manufacturers can reliably plate copper to the required thickness throughout the barrel length. At AR 8:1–10:1, advanced plating chemistry and tighter process control are needed. At AR > 10:1, uniform copper deposition becomes difficult, leading to thin spots in the barrel center, increased resistance, and potential open failures. Microvias — laser-drilled vias with diameter ≤ 150 µm — have a special aspect ratio limit of 0.8:1 because they are filled rather than plated, and depth is limited by laser capability.
Annular Ring and IPC Density Levels
The annular ring is the copper ring on a pad that surrounds the drilled hole. It provides the mechanical bond between the pad and the via barrel, and it must be wide enough to ensure reliable soldering and electrical connection even when drill registration is slightly off. IPC-2221 specifies minimum annular ring widths based on fabrication class and IPC density level. Level A (general electronics) allows larger tolerances with minimum pad sizes 0.6 mm beyond the maximum drill diameter. Level B (moderate density) requires pads 0.5 mm beyond drill. Level C (high-density HDI) targets 0.4 mm beyond drill. Always verify your fab shop's specific capabilities, as tighter rules may apply.
Via Types and Their Applications
Through-hole vias penetrate the full board thickness and are the lowest-cost option. Blind vias connect an outer layer to one or more inner layers without penetrating all the way through, enabling shorter signal paths and greater routing density at moderate extra cost. Buried vias connect inner layers only and are invisible from outer surfaces; they require sequential lamination, making them the most expensive option, typically reserved for high-density interconnect designs. Microvias are laser-drilled holes with diameters of 0.05–0.15 mm used in HDI boards for fine-pitch BGA routing. Via-in-pad places a via under a component pad, requiring the via to be filled and capped to prevent solder from wicking into the hole.
Formulas
Current capacity in amperes, where k = 0.093 for external/through-hole layers (0.048 for internal), ΔT is allowable temperature rise in °C, and A is the copper barrel cross-sectional area in square mils: A = π × D_drill(mils) × t_plating(mils).
DC resistance of the via barrel in ohms, where ρ is copper resistivity (1.724 × 10⁻⁸ Ω·m at 20°C), h is the via height (board thickness) in meters, and A is the barrel cross-sectional area in m². Temperature-corrected resistance: R_T = R_20 × [1 + 0.00393 × (T - 20)].
Approximate self-inductance of a via in nanohenries, where h is via height in mm and d is drill diameter in mm. At 1 GHz, each nanohenry contributes approximately 6.3 Ω of impedance.
Board thickness (h) divided by finished drill diameter (d), both in the same units. AR ≤ 8:1 is standard manufacturing; 8–10:1 requires advanced plating; >10:1 is difficult to plate uniformly.
Reference Tables
Standard Via Sizes and Current Capacity (25 µm plating, 10°C rise)
| Via Name | Drill (mm) | Barrel Area (mil²) | IPC-2221 Max Current (A) | Typical Use |
|---|---|---|---|---|
| Microvia | 0.10 | 3.1 | 0.23 | HDI, fine-pitch BGA escape |
| Small | 0.20 | 6.2 | 0.39 | Signal vias, moderate density |
| Standard | 0.30 | 9.3 | 0.53 | General purpose signal and power |
| Large | 0.40 | 12.4 | 0.65 | Power connections, ground stitching |
| Power | 0.50 | 15.5 | 0.76 | High-current power delivery |
IPC-2221 Minimum Annular Ring Requirements
| IPC Density Level | Fab Tolerance (mm) | Min Annular Ring — External | Min Annular Ring — Internal |
|---|---|---|---|
| Level A (General) | 0.6 | 0.15 mm (6 mil) | 0.10 mm (4 mil) |
| Level B (Moderate) | 0.5 | 0.13 mm (5 mil) | 0.08 mm (3 mil) |
| Level C (HDI) | 0.4 | 0.10 mm (4 mil) | 0.05 mm (2 mil) |
Worked Examples
Standard Via Current Capacity Check
Convert to mils: D_drill = 0.3 mm = 11.81 mil, t_plating = 25 µm = 0.984 mil
Barrel cross-section: A = π × 11.81 × 0.984 = 36.5 mil²
IPC-2221 formula: I = 0.093 × 10^0.44 × 36.5^0.75
I = 0.093 × 2.754 × 14.93 = 3.82 A... (Note: using exact IPC constants)
Check aspect ratio: AR = 1.6 / 0.3 = 5.33:1 — within safe range (≤ 8:1)
Via Array for 5A Power Connection
Single via capacity at 10°C rise: ~0.53 A (from IPC-2221)
Minimum vias needed: 5.0 / 0.53 = 9.4 → round up to 10 vias
For robust design (0.5 A/via target): 5.0 / 0.5 = 10 vias
Total array resistance: R_single / N = 2.48 mΩ / 10 = 0.248 mΩ
Voltage drop: V = 5 A × 0.000248 Ω = 1.24 mV
Power loss: P = 5² × 0.000248 = 6.2 mW
Microvia Aspect Ratio Check
Aspect ratio: AR = 0.08 / 0.10 = 0.8:1
Microvia limit per IPC: AR ≤ 0.8:1 (filled via, laser-drilled)
This is exactly at the limit — acceptable for most HDI fabricators
Verify with your specific fab house, as some allow up to 1.0:1
How to Use the PCB Via Size Calculator
Select Via Type and Enter Geometry
Choose through-hole, blind, buried, or microvia from the Via Type dropdown — this selects the correct IPC-2221 formula constants. Then enter the finished drill diameter in millimeters (use the preset buttons for standard sizes), plating thickness (25 µm standard), and board thickness (1.6 mm is the most common 4-layer board). The calculator updates results instantly as you type.
Set Thermal and Electrical Parameters
Enter the allowable temperature rise (10°C is the IPC standard default; up to 20–30°C may be acceptable for power connections) and ambient operating temperature. If you have a current requirement, enter it in the Required Current field to see the pass/fail status and safety margin. For via arrays, enter the number of parallel vias to calculate total current capacity and total resistance.
Check Pad Diameter and Annular Ring
Expand the Pad & Annular Ring section and enter your pad diameter to verify that your annular ring meets IPC-2221 minimums (6 mil external, 4 mil internal). Select the IPC density level matching your board class. The calculator shows the minimum recommended pad diameter for your drill size and IPC level, making it easy to determine the correct pad size during layout.
Review Results and Export
Review current capacity, resistance, voltage drop, power loss, thermal resistance, aspect ratio risk, and the via size comparison chart. Toggle the Copper Plane connection if your via is adjacent to a copper pour to see the IPC-2152 rating. Enable Advanced parameters to see via inductance and capacitance for high-speed designs. Export to CSV for documentation or click Print to generate a printable report.
Frequently Asked Questions
What is the IPC-2221 formula for via current capacity?
The IPC-2221 standard formula for via current capacity is I = k × ΔT^0.44 × A^0.75, where I is the current in amperes, ΔT is the allowable temperature rise above ambient in degrees Celsius, and A is the copper barrel cross-sectional area in square mils. For through-hole vias, k = 0.093. For blind and buried vias (inner-layer copper), k is lower because inner copper dissipates heat less efficiently. The barrel area is calculated as π × drill_diameter × plating_thickness, representing the annular copper ring, not the full hole area. The formula was derived empirically from physical testing of plated-through holes at IPC and is the global industry standard for via sizing.
What aspect ratio should I target for reliable manufacturing?
For standard PCB manufacturing, target an aspect ratio (board thickness ÷ drill diameter) of 8:1 or less. Most PCB fabricators can reliably plate copper into holes with aspect ratios up to 8:1 using standard chemistry. Aspect ratios between 8:1 and 10:1 are achievable but require advanced plating processes and may incur a cost premium. Aspect ratios above 10:1 are difficult to plate uniformly — the barrel center receives insufficient copper, creating thin spots that increase resistance and risk of open failures. For microvias (laser-drilled HDI vias), the target is 0.8:1 or less, with a maximum depth of approximately 0.25 mm. Always confirm the maximum aspect ratio with your specific fabricator before finalizing the design.
How many vias do I need for a power connection?
The minimum number of vias for a power connection depends on the current requirement and the current capacity of each individual via. A good design rule is to size your via array so each via carries no more than 0.5–1 A, providing substantial safety margin. For example, if you need to carry 5 A through a 1.6 mm board with standard 0.3 mm drills and 25 µm plating at a 10°C temperature rise, each via has a capacity of approximately 0.7 A, so you would need at least 8 vias (5 A ÷ 0.7 A = 7.1, round up). Use the Design Vias mode in this calculator to automatically determine the minimum via count for your target current. Arrange power vias in a grid pattern for even current distribution.
What is the difference between IPC-2221 and IPC-2152 current ratings?
IPC-2221 provides conservative current ratings for isolated conductors without accounting for heat spreading to adjacent copper. IPC-2152 is a newer standard that explicitly accounts for copper plane connections, which provide additional heat-sinking and dramatically improve current capacity. When a via barrel contacts or is adjacent to a large copper plane (ground or power plane), the plane absorbs heat dissipated in the via, allowing the via to carry approximately 1.2 times more current than the IPC-2221 rating. Toggle the Copper Plane option in this calculator to see the IPC-2152 rating. Always use IPC-2221 as your baseline for isolated signal vias, and IPC-2152 only for vias directly connected to large copper fills.
What is via inductance and when does it matter?
Via self-inductance is a parasitic property that causes the via to resist changes in current at high frequencies, creating impedance proportional to frequency. The inductance of a via is approximately 0.2 × h × [ln(4h/d) + 1] nanohenries, where h is the via height in millimeters and d is the drill diameter. As a rule of thumb, expect about 1 nH per millimeter of via length in standard FR-4. At 1 GHz, 1 nH produces about 6 ohms of impedance — significant compared to 50-ohm trace impedance. For designs above 500 MHz, via inductance becomes important for signal integrity. Minimize via inductance by using shorter vias (thinner boards or blind vias), larger drill diameters, and via-in-pad techniques. Add the inductance value from this calculator to your simulation models for accurate high-speed analysis.
What is the minimum annular ring, and why does it matter?
The annular ring is the copper ring on a pad that surrounds the via drill hole on each layer. IPC-2221 specifies minimum annular ring widths to ensure reliable manufacturing even when drill registration is slightly off-center. For external layers (Class 2 and 3 boards), the minimum annular ring is 6 mils (0.15 mm). For internal layers and buried vias, the minimum is 4 mils (0.10 mm). If the drill wanders outside this ring during fabrication, the via may lose its electrical connection to that layer — a catastrophic open failure. Tighter fabrication tolerances (IPC Level C) allow smaller pads, which is essential for high-density routing around fine-pitch BGA components. Always leave at least 6 mils of annular ring on external layers to ensure manufacturing yield.